Asynchronous circuit

An asynchronous circuit is a digital circuit whose state changes are coordinated by signals or local handshakes rather than a shared clock. Its components communicate when events occur instead of waiting for clock edges.

Handshake circuit: A circuit that coordinates data transfer through request and acknowledgment signals. Request and acknowledgment signals provide a common way for asynchronous blocks to agree that a transfer is complete.
Event-driven computation: A model of computation in which actions occur in response to events rather than fixed time steps. Asynchronous circuits use event-driven behavior instead of globally scheduled clock cycles.
Asynchronous microprocessor: A processor whose internal operations are coordinated without a single global clock. Processors show how asynchronous handshakes can coordinate instruction execution and data movement.
Synchronous circuit: A digital circuit whose state changes are coordinated by a shared clock signal. It is the direct alternative, using clock edges where asynchronous circuits use event coordination.
David E. Muller: An American computer scientist who helped establish foundational theories of asynchronous circuits. Muller's work shaped the formal understanding of circuits whose behavior depends on event ordering.
Four-phase handshake: A handshake protocol in which request and acknowledgment each rise and return low during a transfer. Its four transitions make completion explicit without relying on a clock.
Completion detection: The detection that all required operations or data signals have reached a valid completed state. A circuit often needs completion detection before it can safely begin its next operation.
Clockless integrated circuit: An integrated circuit that operates without a global clock signal. This is a broad implementation target for asynchronous circuit techniques.
Clock signal: A periodic electrical signal used to coordinate operations in synchronous digital systems. A shared clock supplies the timing reference that this circuit design omits.
Speed-independent circuit: An asynchronous circuit designed to work correctly under arbitrary gate delays, assuming negligible wire delays. This model captures an influential middle ground between ideal delay independence and practical timing assumptions.

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