Cache coherence

Cache coherence is the set of rules and protocols that keep cached copies of the same memory location consistent across processors. It ensures that processors observe writes to shared data in a coherent order.

MESI protocol: A cache-coherence protocol with Modified, Exclusive, Shared, and Invalid states for each cache line. Its four states show how caches track ownership and sharing of a line.
Cache memory: Small, fast storage that keeps copies of data likely to be reused by a processor. Coherence becomes necessary when private caches can hold copies of shared memory.
Symmetric multiprocessing: A computer architecture in which multiple peer processors share memory and operating-system responsibilities. SMP systems rely on coherence to make shared-memory data usable across processors.
Write-through cache: A cache policy that sends every cache write to the next lower level of the memory hierarchy. Write-through simplifies propagation but does not by itself coordinate other processors’ copies.
Cache coherence traffic: Interconnect messages generated to maintain consistent cached copies in a multiprocessor. Invalidations and ownership transfers consume bandwidth as shared data is accessed.
MOESI protocol: A cache-coherence protocol that adds an Owned state to MESI, allowing a modified line to be shared without immediate writeback. The Owned state reduces memory traffic while preserving a coherent shared copy.
Shared memory: A memory model in which multiple processors can access a common address space. Shared addresses allow different caches to contain copies of the same data.
Multicore processor: A processor containing multiple cores that can execute instruction streams concurrently. Private core caches create coherence traffic even within one chip.
Write-back cache: A cache policy that delays lower-level memory updates until a modified line is evicted or explicitly written back. Write-back saves bandwidth but makes coherent ownership and dirty data essential.
Cache-coherence overhead: Performance and energy costs caused by communication and state tracking for coherent caches. Frequent sharing can make coherence costs outweigh the benefit of local caching.

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