Clock-domain crossing

Clock-domain crossing is the transfer of signals between synchronous circuit regions governed by different clocks. It can cause metastability, missed transitions, or corrupted multi-bit data unless the transfer is designed for them.

Metastability (electronics): A temporary unstable state in a bistable circuit, caused when its input changes near a sampling edge. An asynchronous transition can leave a destination flip-flop metastable.
Clock signal: A periodic electrical signal used to coordinate state changes in digital circuits. Each domain uses clock edges to determine when its sequential logic updates.
Pulse synchronizer: A circuit that transfers a brief event between clock domains while ensuring the destination detects it. A simple level synchronizer can miss pulses shorter than a destination clock period.
Synchronous clock domain: A group of sequential circuit elements governed by the same clock or a precisely related clock. Transfers inside one domain can usually be analyzed with ordinary synchronous timing.
Synchronizer (digital electronics): A circuit, commonly a chain of flip-flops, that reduces the chance metastability propagates into synchronous logic. A two-flop synchronizer is the basic remedy for single-bit crossings.
Flip-flop (electronics): A bistable circuit that stores one bit and changes state in response to control inputs. Clocked flip-flops sample signals and are the sites where metastability can arise.
Multi-cycle path: A timing path allowed more than one clock cycle for its data to reach the destination. A declared timing exception does not make an asynchronous crossing safe.
Asynchronous circuit: A digital circuit whose operation does not depend on a global clock signal. Clock-domain crossing joins clocked regions; it is not the same as wholly asynchronous design.
Asynchronous FIFO: A first-in, first-out buffer that uses separate clocks for writing and reading data. It transfers multi-bit streams while decoupling the clocks on each side.
Setup time: The minimum time an input must remain stable before a clock edge for reliable sampling. Cross-domain signals cannot guarantee setup time at the destination clock edge.

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