Clock skew

Clock skew is the difference in arrival time of the same clock edge at different points in a circuit. It can reduce timing margins or cause sequential logic to capture data incorrectly.

Clock tree: A network of buffers and wires that distributes a clock signal to sequential elements in a circuit. Unequal paths through this network are a common source of arrival-time differences.
Static timing analysis: A method for checking circuit timing by analyzing paths and timing constraints without simulating input sequences. It evaluates skew's effect on setup and hold slack across timing paths.
Clock-tree synthesis: The automated design step that builds a clock distribution network to meet skew, latency, and load constraints. Its buffers and routing are selected to control arrival-time differences.
Clock jitter: Short-term variation in the timing of clock edges relative to their ideal positions. Jitter shifts edges over time; skew compares arrival times across circuit locations.
Clock-to- Q delay: The time between a triggering clock edge at a flip-flop and the resulting change at its output. This delay combines with skew to determine when launched data reaches the next register.
Setup violation: A timing failure in which data does not arrive early enough to satisfy a sequential element's setup requirement. Late capture clocks can help setup timing, while early capture clocks can cause this failure.
Clock distribution network: The circuitry and interconnect that deliver clock signals to sequential elements across a chip. Clock skew is a key timing property of this broader network.
Clock phase: The position of a periodic signal within its cycle relative to a reference. Phase describes a signal's cycle position, while skew compares edge arrival across endpoints.
Setup time: The minimum time input data must remain stable before a clock edge at a sequential element. Positive skew can lengthen the available setup interval between launch and capture.
Hold violation: A timing failure in which data changes too soon after a clock edge to satisfy a sequential element's hold requirement. Late capture clocks can make this failure more likely.

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