Computer architecture

Computer architecture is the design and organization of a computer system, including its instruction set, processor, memory, and interfaces. It describes the structure and behavior visible to software and the mechanisms that implement them.

Instruction set architecture: The programmer-visible specification of a processor, including its instructions, registers, and memory model. It defines the contract between software and the processor’s implementation.
Instruction cycle: The sequence of fetching, decoding, and executing a machine instruction. It describes the basic process through which architectural instructions take effect.
Reduced instruction set computer: A processor design approach based on a relatively small set of simple instructions. It contrasts with complex instruction set designs in how work is expressed and executed.
Computer performance: The rate at which a computer completes work, measured through metrics such as latency and throughput. Architectural choices determine how quickly instructions and workloads complete.
Central processing unit: The processor that executes instructions and coordinates operations within a computer. Its datapath and control logic implement the architecture’s instruction set.
Pipelining: A technique that overlaps successive stages of instruction processing. It raises throughput by allowing multiple instructions to occupy different stages at once.
Complex instruction set computer: A processor design approach that provides instructions capable of performing complex operations. Its richer instructions offer a different trade-off from reduced instruction set designs.
Power efficiency: The amount of useful computation delivered per unit of electrical energy. Processor and memory organization constrain performance under energy and heat limits.
Computer memory: Hardware that stores data and instructions for a computer to use. Its capacity, speed, and organization shape how programs access data.
Cache hierarchy: A layered organization of memory caches with different capacities and access speeds. It reduces average access time by keeping frequently used data near the processor.

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