Knowra Instruction cycle Instruction cycle The recurring sequence in which a processor fetches an instruction, decodes it, and carries out the required operation. Its stages may overlap or be divided into finer steps in modern processors.
Instruction fetch : The stage in which a processor retrieves an instruction from memory or an instruction cache. This begins each instruction's passage through the cycle.
Machine instruction : A binary-encoded command that specifies an operation and, often, its operands. Each cycle processes one machine instruction or a portion of one.
Instruction pipelining : A processor technique that overlaps stages of multiple instructions to increase throughput. It lets fetch, decode, and execution proceed concurrently for different instructions.
Single-cycle processor : A processor design that completes every instruction in one clock cycle. It makes the cycle a literal single clock period, unlike staged implementations.
Instruction decode : The stage in which a processor interprets an instruction's operation and identifies its operands. Decoding determines what work the fetched instruction requires.
Instruction set architecture : The programmer-visible specification of a processor's instructions, registers, and memory behavior. It defines what instructions the cycle must interpret and support.
Superscalar processor : A processor that can issue and execute multiple instructions in one clock cycle. It runs several instruction paths at once instead of advancing only one per cycle.
Multicycle processor : A processor design that completes an instruction across multiple clock cycles, reusing hardware between stages. It separates the cycle's work over time instead of requiring one long clock period.
Instruction execution : The stage in which processor hardware performs an instruction's operation. Execution carries out the action selected during decoding.
Register file : A processor's collection of registers used to hold operands, addresses, and intermediate results. Decoded instructions commonly read their inputs from these fast storage locations.
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