Instruction set architecture

An instruction set architecture (ISA) is the programmer-visible specification of a processor, defining its instructions, registers, data types, and memory behavior. It forms the boundary between software and processor implementations.

Machine code: Binary instructions and data encoded for execution by a processor. An ISA specifies how instruction bit patterns are interpreted.
Instruction cycle: The repeating process by which a processor fetches, decodes, and executes instructions. It describes how an ISA instruction becomes processor activity.
Reduced instruction set computer: A processor design approach built around a relatively small set of simple instructions. RISC designs favor simple instruction forms, unlike many complex-instruction designs.
x86: A family of instruction set architectures originating with Intel's 8086 processor. It is a long-lived ISA family used in personal computers and servers.
Registers: Small, fast storage locations within a processor, directly named by machine instructions. An ISA defines the registers that software can access.
Instruction decoding: The process of interpreting encoded instruction bits to determine an operation and its operands. A processor decodes machine code according to its ISA.
Complex instruction set computer: A processor design approach with instructions that can perform relatively complex operations. CISC designs offer richer instruction behavior than a typical RISC approach.
ARM architecture: A family of instruction set architectures developed by Arm for processors across many device classes. Its implementations span phones, embedded systems, laptops, and servers.
Instruction set: The collection of operations a processor can execute, represented by encoded instructions. It is the ISA's central vocabulary of operations.
Microarchitecture: The internal organization and implementation of a processor that realizes an instruction set architecture. Different microarchitectures can implement the same ISA.

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