Network on a chip

A network on a chip is an on-chip communication system that connects processor cores, memory, and other components through routers and links. It replaces or supplements dedicated point-to-point wiring with structured packet-based communication.

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On-chip router: A switching component that forwards packets between network-on-chip links and connected components. Routers direct packets through the fabric and arbitrate among competing transfers.
Network endpoint: An interface that connects a component to a communication network and adapts its data to network transfers. Endpoints let cores and peripherals inject and receive network traffic.
Crossbar switch: A switching structure that can connect any input to any output through a grid of crosspoints. A crossbar offers direct paths but its wiring and switch cost grow rapidly with port count.
Manycore processor: A processor containing a large number of cores designed to execute tasks in parallel. Manycore chips need scalable communication among numerous cores and shared resources.
Deadlock (computer science): A state in which processes or transactions wait indefinitely for resources held by one another. Routing and resource allocation must prevent packets from forming cyclic waits.
Wormhole switching: A packet-switching method that divides packets into flits and lets them occupy multiple routers along a path. It limits buffering needs while making congestion and blocked paths consequential.
Network interface controller: Hardware that manages communication between a computing component and a network. Its on-chip form translates component transactions into network packets.
Bus (computing): A shared communication pathway that carries signals among multiple computing components. A bus is simpler for small systems but shared access limits concurrent transfers.
Tiled multiprocessor: A processor organized as repeated tiles, each containing processing and often communication resources. A network on a chip can connect the repeated tiles without requiring a global shared bus.
Quality of service: Methods for controlling network performance characteristics such as latency, bandwidth, and priority. On-chip traffic may mix latency-sensitive control messages with high-volume data flows.