Very long instruction word

A processor architecture that groups multiple operations into one long instruction, with the compiler scheduling those operations for parallel execution.

Instruction-level parallelism: The execution of multiple independent instructions during overlapping or shared clock cycles. VLIW exposes instruction-level parallelism by placing independent operations together in one instruction.
Compiler: Software that translates source code into executable instructions for a target machine. A VLIW compiler performs much of the scheduling work that other architectures assign to hardware.
Superscalar processor: A processor that can issue multiple instructions per cycle, typically selecting them dynamically in hardware. Superscalar processors find parallel instructions at runtime; VLIW relies mainly on compiler scheduling.
Texas Instruments TMS320C6x: A family of digital signal processors from Texas Instruments that uses a VLIW architecture. The C6x family is a prominent commercial example of compiler-scheduled parallel operations.
Compiler optimization: Transformations that improve a program’s execution while preserving its specified behavior. VLIW performance depends heavily on compiler ability to identify and schedule useful parallel work.
Static scheduling: The assignment of operations to execution times before a program runs, usually by a compiler. VLIW compilers schedule operations ahead of execution rather than relying on dynamic hardware scheduling.
Data dependency: A relationship in which one operation needs a value produced or modified by another operation. Dependent operations cannot generally occupy parallel slots in the same VLIW bundle.
Out-of-order execution: A processor technique that executes ready instructions before earlier stalled instructions while preserving architectural results. Dynamic reordering handles some dependencies in hardware, unlike VLIW’s largely static schedule.
Itanium: A family of Intel and Hewlett-Packard processors implementing the Explicitly Parallel Instruction Computing architecture. Itanium illustrates a related attempt to expose parallelism through compiler-formed instruction bundles.
Code density: The amount of useful program functionality represented per unit of machine-code storage. Wide instruction words can contain unused slots, increasing code size when parallel work is scarce.

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